Ferroelectric, non-volatile memories have memory cells consisting of a select, or access, transistor, and a storage capacitor whose dielectric is formed by a film of ferroelectric material. The select transistor and the storage capacitor are connected in series.
By applying an electric field of sufficient intensity to the storage capacitor, the ferroelectric material is polarized in the direction of the electric field, and the resulting polarization is maintained also after the removal of the electric field. If, subsequently, an electric field of sufficient intensity and direction opposite to the polarization direction is applied, the ferroelectric material becomes and remains polarized in such opposed direction also after the removal of the electric field. The polarization of the ferroelectric material has the effect of producing a non-zero electric charge for unit area in the storage capacitor, charge that persists also when no voltage is applied to the capacitor, and that does not disappear in time.
A binary information (bit) can thus be stored in the memory cell, by associating the two logic states “1” and “0” to the two opposite polarization directions of the ferroelectric material storage capacitor.
Ferroelectric memories are also called ferroelectric RAMs or FeRAMs, due to the similarity of their memory cells with those of a dynamic RAM memory (DRAM).
Two families of FeRAMs are known, differing from each other in the number of memory cells employed for storing a single bit.
The FeRAMs belonging to a first family use a single memory cell as a bit storage unit, and for this reason they are also called “1T1C” (one transistor, one capacitor). Thanks to the simplicity of the bit storage unit, these memories can have very large size, of the order of the megabits.
A second family of FeRAMs uses two memory cells as a bit storage unit; for this reason, the FeRAMs of this second family are called “2T2C” (two transistors, two capacitors).
As in other memory devices, also in the FeRAMs the memory cells are arranged by rows and columns to form a matrix. For instance, considering the 1T1C FeRAMs, each memory cell has the gate of the respective select transistor connected to a word line of the matrix, the drain of the select transistor connected to a bit line of the matrix, and the free plate of the respective storage capacitor connected to a plate biasing line of the matrix.
According to a convenient arrangement of the matrix, the memory cells belonging to a same matrix row share the same word line and the same plate line; the memory cells belonging to a same matrix column share the same bit line.
A memory location is formed by a group of memory cells, for instance four, eight, sixteen or more, depending on the degree of parallelism of the memory. Typically, the memory cells forming a given location belong to the same row of the matrix.
Each row of the matrix includes several memory locations; the choice of the number of locations on the single row, and, therefore, the choice of the row length, depends on the requirements for the memory in terms of access time, area and current consumption.
To limit such problems, the prior art limits the number of memory locations belonging to a same row of the matrix. However, this is not particularly desirable, because it imposes limitations on the dimensions of matrices.
Similar problems are also encountered in the 2T2C FeRAMs.